FURI | Summer 2025

VeriLLM: a Large Language Model-Driven Toolchain for Enhanced Verilog Workflow Optimization

This project develops VeriLLM (Verilog-enhanced Large Language Model), a toolchain to advance Verilog-based hardware design through large language models. VeriLLM’s agentic framework automates code generation and debugging, streamlining workflows for engineers. Evaluations show enhanced efficiency and accessibility in hardware design processes. Future work includes refining training procedures and expanding integration with diverse design tools to further optimize performance.