FURI | Spring 2024

Optimizing Compact Model of Nanosheet FET (NSFET) for Analog/Digital IC Design

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The Nanosheet FET (NSFET) demonstrates superior performance, emerging as a leading option for 3 nm technology and beyond. Despite its potential, the wide adoption of NSFET is limited by reliability issues like transconductance degradation from gate length scaling, parasitics from channel height and geometry of nanosheets, thermal effects, and process variations. To address these challenges and aid circuit design and simulation, in this project, the researcher develops an optimized machine-learning (ML) assisted compact model, leveraging the MIT Virtual Source model. This model, designed for easy integration into commercial circuit simulation tools, facilitates device-level optimization and overall performance improvement.

Student researcher

Po-Heng Ho

Electrical engineering

Hometown: Tempe, Arizona, United States

Graduation date: Spring 2024