Guest Researcher | Spring 2025

Improving Hardware Verification Coverage Using LLMs

Hardware verification is one of the most challenging stages of the hardware design process due to the time and resources required to ensure a design is thoroughly verified and production-ready. Recent advancements in large language models (LLMs) like ChatGPT-4 and LLaMa 3.3 have demonstrated their potential in assisting digital hardware design and verification. Traditional verification aims to maximize design coverage, often requiring multiple engineers per design engineer. In this work, we present an automated framework leveraging LLaMa 3.3 to generate test cases from design specifications, accelerating coverage closure. We explore multiple interaction strategies, including coverage score feedback, multi-LLM architectures, RAG, and best-of-n generation. Our analysis highlights the potential of LLMs to enhance verification workflows and reduce the manual effort required to achieve high coverage.