FURI | Fall 2024

Improving Hardware Verification Coverage using LLMs

Hardware verification is one of the most challenging stages of the hardware design process because of the time and resources involved in ensuring that a hardware design is fully verified and production-ready. With the drastic increase in the strength of code generation from the most recent generation of large language models (LLMs) like ChatGPT-3.5-turbo and ChatGPT-4 from OpenAI, it has been shown that, especially with well-executed fine-tuning, LLMs are powerful tools for overcoming the difficulties of digital hardware design and verification. In traditional design verification, the goal is to maximize code and functional coverage of the design, which is notoriously difficult for verification engineers, and verification teams typically involve three to five engineers per design engineer. Using an automated few-shot interaction between a fine-tuned LLM and a code coverage analyzer, hardware design test benches that exceed code coverage standards can be quickly generated to rapidly improve the design verification process.