Po-Heng Ho
Electrical engineering
Hometown: Tempe, Arizona, United States
Graduation date: Spring 2024
Additional details: Transfer student
FURI | Spring 2024
Optimizing Compact Model of Nanosheet FET (NSFET) for Analog/Digital IC Design
The Nanosheet FET (NSFET) demonstrates superior performance, emerging as a leading option for 3 nm technology and beyond. Despite its potential, the wide adoption of NSFET is limited by reliability issues like transconductance degradation from gate length scaling, parasitics from channel height and geometry of nanosheets, thermal effects, and process variations. To address these challenges and aid circuit design and simulation, in this project, the researcher develops an optimized machine-learning (ML) assisted compact model, leveraging the MIT Virtual Source model. This model, designed for easy integration into commercial circuit simulation tools, facilitates device-level optimization and overall performance improvement.
Mentor: Kexin Li
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Sponsored project | Spring 2024
Po-Heng Ho’s FURI project is sponsored by TSMC.
TSMC is a global leader in the semiconductor foundry business. The company’s industry-leading process technologies and portfolio of design enablement solutions help its customers and partners unleash semiconductor innovation. With its recent expansion into Phoenix, TSMC sees the benefit of a strong partnership with ASU faculty and student researchers. TSMC supports the FURI program by providing additional funding for exceptional research projects related to the semiconductor industry. FURI student researchers who pursue a project related to the Semiconductor Manufacturing research theme are eligible for this sponsorship. TSMC-supported FURI students receive a $2,600 stipend and $400 to use for materials. Exceptional research proposals that align with the research theme of Semiconductor Manufacturing will be considered for this additional funding.