FURI | Spring 2024

Verification Code Generation in the Hardware Description Language Verilog

The hardware industry employs Verilog and other hardware description languages to design and test a variety of application-specific integrated circuits. The process of verifying a circuit design is non-trivial and requires many resources to ensure functionality. This study attempts to create a machine learning model that generates verification code given a circuit design and its specification document. This tool for verification code generation in Verilog intends to shorten the testing phase of the design process and remove roadblocks engineers face when designing chips. Future work would be to create a larger training data set that incorporates visual abstractions and waveforms.