Deepak Kumar Athur
Computer engineering
Hometown: Chennai, Tamil Nadu, India
Graduation date: Spring 2024
MORE | Spring 2024
Performance Evaluation of TPUs and FPGAs for Deep Neural Network Inference
The high computational complexity of AI algorithms and the stringent cost-energy-latency necessitate the use of efficient domain-specific hardware. With several design choices available from reconfigurable Field Programmable Gate Arrays (FPGAs) to highly specialized Application Specific Integrated Circuits for example Tensor Processing Unit (TPU), it is important to make a meaningful hardware platform choice. This research project aims to evaluate TPU and FPGA for inference by running DNN models on TPUs and an FPGAs and evaluate the following of the devices: Performance (Inferences/second), energy cost per inference, and a flexibility metric to quantize the ability to adapt to newer DNN models.
Mentor: Aman Arora
It’s hip to be square.
Students presenting projects at the Fulton Forge Student Research Expo are encouraged to download this personal QR code and include it within your poster. This allows expo attendees to explore more about your project and about you in the future.
Right click the image to save it to your computer.