FURI | Spring 2025

Conductive Filament Modeling and Reliability Prediction in Pt/SiOx/TiN

Many modern computing designs utilize the von Neumann architecture, where data and program instructions share the same memory bus. This leads to the “von Neumann bottleneck,” reducing efficiency due to the inability to transfer data and instructions simultaneously. A proposed solution lies in resistive random access memory (RRAM), an emerging memory device type that allows multiple data transfer pathways, bypassing the sequential transfer issue. This project aims to model and study the mechanisms and reliability of a CMOS-compatible, oxide-based RRAM device (Pt/SiOx/TiN), with successful results leading to the advancement of the integration of these devices into computing architectures.